In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, available in the algorithms. Our designs are generated with a view of actual hardware/software co-execution on a real hardware platform. The carried experiments on the MOLEN polymorphic processor prototype suggest overall application speedups between 1.4x and 6.8x, corresponding to 13% to 94% of the theoretically achievable maximums, constituted by Amdahl's law.
|Title of host publication||2007 International Conference on Field Programmable Logic and Applications|
|Number of pages||5|
|Publication status||Published - 1-Dec-2007|
|Event||2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands|
Duration: 27-Aug-2007 → 29-Aug-2007
|Conference||2007 International Conference on Field Programmable Logic and Applications, FPL|
|Period||27/08/2007 → 29/08/2007|