DWARV: Delftworkbench automated reconfigurable VHDL generator

Yana Yankova; Georgi Kuzmanov; Koen Bertels; Georgi Gaydadjiev; Yi Lu; Stamatis Vassiliadis

doi:10.1109/FPL.2007.4380748

DWARV: Delftworkbench automated reconfigurable VHDL generator

Yana Yankova^*, Georgi Kuzmanov, Koen Bertels, Georgi Gaydadjiev, Yi Lu, Stamatis Vassiliadis

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

75 Citations (Scopus)

Abstract

In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, available in the algorithms. Our designs are generated with a view of actual hardware/software co-execution on a real hardware platform. The carried experiments on the MOLEN polymorphic processor prototype suggest overall application speedups between 1.4x and 6.8x, corresponding to 13% to 94% of the theoretically achievable maximums, constituted by Amdahl's law.

Original language	English
Title of host publication	2007 International Conference on Field Programmable Logic and Applications
Publisher	IEEE
Pages	697-701
Number of pages	5
ISBN (Print)	978-1-4244-1059-0
DOIs	https://doi.org/10.1109/FPL.2007.4380748
Publication status	Published - 1-Dec-2007
Externally published	Yes
Event	2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands Duration: 27-Aug-2007 → 29-Aug-2007

Conference

Conference	2007 International Conference on Field Programmable Logic and Applications, FPL
Country/Territory	Netherlands
City	Amsterdam
Period	27/08/2007 → 29/08/2007

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@inproceedings{6e7d38957b974fd393d5d48b2445148a,

title = "DWARV: Delftworkbench automated reconfigurable VHDL generator",

abstract = "In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, available in the algorithms. Our designs are generated with a view of actual hardware/software co-execution on a real hardware platform. The carried experiments on the MOLEN polymorphic processor prototype suggest overall application speedups between 1.4x and 6.8x, corresponding to 13% to 94% of the theoretically achievable maximums, constituted by Amdahl's law.",

author = "Yana Yankova and Georgi Kuzmanov and Koen Bertels and Georgi Gaydadjiev and Yi Lu and Stamatis Vassiliadis",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/FPL.2007.4380748",

language = "English",

isbn = "978-1-4244-1059-0",

pages = "697--701",

booktitle = "2007 International Conference on Field Programmable Logic and Applications",

publisher = "IEEE",

note = "2007 International Conference on Field Programmable Logic and Applications, FPL ; Conference date: 27-08-2007 Through 29-08-2007",

}

Yankova, Y, Kuzmanov, G, Bertels, K, Gaydadjiev, G, Lu, Y & Vassiliadis, S 2007, DWARV: Delftworkbench automated reconfigurable VHDL generator. in 2007 International Conference on Field Programmable Logic and Applications., 4380748, IEEE, pp. 697-701, 2007 International Conference on Field Programmable Logic and Applications, FPL, Amsterdam, Netherlands, 27/08/2007. https://doi.org/10.1109/FPL.2007.4380748

TY - GEN

T1 - DWARV

T2 - 2007 International Conference on Field Programmable Logic and Applications, FPL

AU - Yankova, Yana

AU - Kuzmanov, Georgi

AU - Bertels, Koen

AU - Gaydadjiev, Georgi

AU - Lu, Yi

AU - Vassiliadis, Stamatis

PY - 2007/12/1

Y1 - 2007/12/1

N2 - In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, available in the algorithms. Our designs are generated with a view of actual hardware/software co-execution on a real hardware platform. The carried experiments on the MOLEN polymorphic processor prototype suggest overall application speedups between 1.4x and 6.8x, corresponding to 13% to 94% of the theoretically achievable maximums, constituted by Amdahl's law.

AB - In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, available in the algorithms. Our designs are generated with a view of actual hardware/software co-execution on a real hardware platform. The carried experiments on the MOLEN polymorphic processor prototype suggest overall application speedups between 1.4x and 6.8x, corresponding to 13% to 94% of the theoretically achievable maximums, constituted by Amdahl's law.

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U2 - 10.1109/FPL.2007.4380748

DO - 10.1109/FPL.2007.4380748

M3 - Conference contribution

AN - SCOPUS:48149091918

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BT - 2007 International Conference on Field Programmable Logic and Applications

PB - IEEE

Y2 - 27 August 2007 through 29 August 2007

ER -

DWARV: Delftworkbench automated reconfigurable VHDL generator

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