Exploiting SPMD Horizontal Locality

Chunyang Gou*, Georgi N. Gaydadjiev

*Corresponding author for this work

Research output: Contribution to journalArticleAcademicpeer-review

1 Citation (Scopus)


In this paper, we analyze a particular spatial locality case (called horizontal locality) inherent to manycore accelerator architectures employing barrel execution of SPMD kernels, such as GPUs. We then propose an adaptive memory access granularity framework to exploit and enforce the horizontal locality in order to reduce the interferences among accelerator cores memory accesses and hence improve DRAM efficiency. With the proposed technique, DRAM efficiency grows by 1.42X on average, resulting in 12.3% overall performance gain, for a set of representative memory intensive GPGPU applications.

Original languageEnglish
Article number5752788
Pages (from-to)20-23
Number of pages4
JournalIeee computer architecture letters
Issue number1
Publication statusPublished - 2011
Externally publishedYes


  • Memory hierarchy
  • Multi-core/single-chip multiprocessors
  • SIMD processors

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