An implementation of an On Chip Memory (OCM) based Dual Data Rate external memory controller (OCM2DDR) for Virtex II Pro is described. The proposed OCM2DDR controller comprises Data Side OCM (DSOCM) bus interface module, read and write control logic, halt read module and Xilinx DDR controller IP core. The presented design supports 16MB of external DDR memory and 32 to 64 bits data conversion for single read and write operations. Our implementation uses 1063 slices of Virtex2Pro FPGA and runs at 100 MHz. The major benefits of the proposed design are high bandwidth to external memory with reduced and more predictable access times compared to the Xilinx PLB DDR controller implementation. More specially, our read and write accesses are 2,44 and 4,25 times faster, than the PLB based solution respectively.
|Title of host publication||2006 International Symposium on System-on-Chip|
|Publication status||Published - 1-Dec-2006|
|Event||2006 International Symposium on System-on-Chip, SOC - Tampere, Finland|
Duration: 13-Nov-2006 → 16-Nov-2006
|Conference||2006 International Symposium on System-on-Chip, SOC|
|Period||13/11/2006 → 16/11/2006|