External memory controller for Virtex II Pro

Blagomir Donchev; Georgi Kuzmanov; Georgi N. Gaydadjiev

doi:10.1109/ISSOC.2006.322009

External memory controller for Virtex II Pro

Blagomir Donchev^*, Georgi Kuzmanov, Georgi N. Gaydadjiev

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

8 Citations (Scopus)

Abstract

An implementation of an On Chip Memory (OCM) based Dual Data Rate external memory controller (OCM2DDR) for Virtex II Pro is described. The proposed OCM2DDR controller comprises Data Side OCM (DSOCM) bus interface module, read and write control logic, halt read module and Xilinx DDR controller IP core. The presented design supports 16MB of external DDR memory and 32 to 64 bits data conversion for single read and write operations. Our implementation uses 1063 slices of Virtex2Pro FPGA and runs at 100 MHz. The major benefits of the proposed design are high bandwidth to external memory with reduced and more predictable access times compared to the Xilinx PLB DDR controller implementation. More specially, our read and write accesses are 2,44 and 4,25 times faster, than the PLB based solution respectively.

Original language	English
Title of host publication	2006 International Symposium on System-on-Chip
Publisher	IEEE
ISBN (Print)	9781-4244-0621-8
DOIs	https://doi.org/10.1109/ISSOC.2006.322009
Publication status	Published - 1-Dec-2006
Externally published	Yes
Event	2006 International Symposium on System-on-Chip, SOC - Tampere, Finland Duration: 13-Nov-2006 → 16-Nov-2006

Conference

Conference	2006 International Symposium on System-on-Chip, SOC
Country/Territory	Finland
City	Tampere
Period	13/11/2006 → 16/11/2006

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@inproceedings{bab3d1ffcea343978599da0f50f71f73,

title = "External memory controller for Virtex II Pro",

abstract = "An implementation of an On Chip Memory (OCM) based Dual Data Rate external memory controller (OCM2DDR) for Virtex II Pro is described. The proposed OCM2DDR controller comprises Data Side OCM (DSOCM) bus interface module, read and write control logic, halt read module and Xilinx DDR controller IP core. The presented design supports 16MB of external DDR memory and 32 to 64 bits data conversion for single read and write operations. Our implementation uses 1063 slices of Virtex2Pro FPGA and runs at 100 MHz. The major benefits of the proposed design are high bandwidth to external memory with reduced and more predictable access times compared to the Xilinx PLB DDR controller implementation. More specially, our read and write accesses are 2,44 and 4,25 times faster, than the PLB based solution respectively.",

author = "Blagomir Donchev and Georgi Kuzmanov and Gaydadjiev, {Georgi N.}",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/ISSOC.2006.322009",

language = "English",

isbn = "9781-4244-0621-8",

booktitle = "2006 International Symposium on System-on-Chip",

publisher = "IEEE",

note = "2006 International Symposium on System-on-Chip, SOC ; Conference date: 13-11-2006 Through 16-11-2006",

}

TY - GEN

T1 - External memory controller for Virtex II Pro

AU - Donchev, Blagomir

AU - Kuzmanov, Georgi

AU - Gaydadjiev, Georgi N.

PY - 2006/12/1

Y1 - 2006/12/1

N2 - An implementation of an On Chip Memory (OCM) based Dual Data Rate external memory controller (OCM2DDR) for Virtex II Pro is described. The proposed OCM2DDR controller comprises Data Side OCM (DSOCM) bus interface module, read and write control logic, halt read module and Xilinx DDR controller IP core. The presented design supports 16MB of external DDR memory and 32 to 64 bits data conversion for single read and write operations. Our implementation uses 1063 slices of Virtex2Pro FPGA and runs at 100 MHz. The major benefits of the proposed design are high bandwidth to external memory with reduced and more predictable access times compared to the Xilinx PLB DDR controller implementation. More specially, our read and write accesses are 2,44 and 4,25 times faster, than the PLB based solution respectively.

AB - An implementation of an On Chip Memory (OCM) based Dual Data Rate external memory controller (OCM2DDR) for Virtex II Pro is described. The proposed OCM2DDR controller comprises Data Side OCM (DSOCM) bus interface module, read and write control logic, halt read module and Xilinx DDR controller IP core. The presented design supports 16MB of external DDR memory and 32 to 64 bits data conversion for single read and write operations. Our implementation uses 1063 slices of Virtex2Pro FPGA and runs at 100 MHz. The major benefits of the proposed design are high bandwidth to external memory with reduced and more predictable access times compared to the Xilinx PLB DDR controller implementation. More specially, our read and write accesses are 2,44 and 4,25 times faster, than the PLB based solution respectively.

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U2 - 10.1109/ISSOC.2006.322009

DO - 10.1109/ISSOC.2006.322009

M3 - Conference contribution

AN - SCOPUS:50049106595

SN - 9781-4244-0621-8

BT - 2006 International Symposium on System-on-Chip

PB - IEEE

T2 - 2006 International Symposium on System-on-Chip, SOC

Y2 - 13 November 2006 through 16 November 2006

ER -

External memory controller for Virtex II Pro

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