Hartes Toolchain Early Evaluation: Profiling, Compilation and HDL Generation

Koen Bertels*, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis Vassiliadis

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

6 Citations (Scopus)


The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedded processor, digital signal processing and reconfigurable hardware. In this paper, we evaluate three tools from the hArtes toolchain supporting profiling, compilation, and HDL generation. These tools facilitate the HW/SW partitioning, co-design, co-verification, and co-execution of demanding embedded applications. The described tools are provided by the DelftWorkBench framework1. Experimental results on MJPEG and G721 encoder application case studies suggest overall performance improvement of 228% and 36% respectively.

Original languageEnglish
Title of host publication2007 International Conference on Field Programmable Logic and Applications
Number of pages7
ISBN (Print)978-1-4244-1059-0
Publication statusPublished - 1-Dec-2007
Externally publishedYes
Event2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands
Duration: 27-Aug-200729-Aug-2007


Conference2007 International Conference on Field Programmable Logic and Applications, FPL

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