Hartes Toolchain Early Evaluation: Profiling, Compilation and HDL Generation

Koen Bertels; Georgi Kuzmanov; Elena Moscu Panainte; Georgi Gaydadjiev; Yana Yankova; Vlad Mihai Sima; Kamana Sigdel; Roel Meeuws; Stamatis Vassiliadis

doi:10.1109/FPL.2007.4380680

Hartes Toolchain Early Evaluation: Profiling, Compilation and HDL Generation

Koen Bertels^*, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis Vassiliadis

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

6 Citations (Scopus)

Abstract

The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedded processor, digital signal processing and reconfigurable hardware. In this paper, we evaluate three tools from the hArtes toolchain supporting profiling, compilation, and HDL generation. These tools facilitate the HW/SW partitioning, co-design, co-verification, and co-execution of demanding embedded applications. The described tools are provided by the DelftWorkBench framework¹. Experimental results on MJPEG and G721 encoder application case studies suggest overall performance improvement of 228% and 36% respectively.

Original language	English
Title of host publication	2007 International Conference on Field Programmable Logic and Applications
Publisher	IEEE
Pages	402-408
Number of pages	7
ISBN (Print)	978-1-4244-1059-0
DOIs	https://doi.org/10.1109/FPL.2007.4380680
Publication status	Published - 1-Dec-2007
Externally published	Yes
Event	2007 International Conference on Field Programmable Logic and Applications, FPL - Amsterdam, Netherlands Duration: 27-Aug-2007 → 29-Aug-2007

Conference

Conference	2007 International Conference on Field Programmable Logic and Applications, FPL
Country/Territory	Netherlands
City	Amsterdam
Period	27/08/2007 → 29/08/2007

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@inproceedings{019341428830450eb5bc750d531a11da,

title = "Hartes Toolchain Early Evaluation: Profiling, Compilation and HDL Generation",

abstract = "The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedded processor, digital signal processing and reconfigurable hardware. In this paper, we evaluate three tools from the hArtes toolchain supporting profiling, compilation, and HDL generation. These tools facilitate the HW/SW partitioning, co-design, co-verification, and co-execution of demanding embedded applications. The described tools are provided by the DelftWorkBench framework1. Experimental results on MJPEG and G721 encoder application case studies suggest overall performance improvement of 228% and 36% respectively.",

author = "Koen Bertels and Georgi Kuzmanov and Panainte, {Elena Moscu} and Georgi Gaydadjiev and Yana Yankova and Sima, {Vlad Mihai} and Kamana Sigdel and Roel Meeuws and Stamatis Vassiliadis",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/FPL.2007.4380680",

language = "English",

isbn = "978-1-4244-1059-0",

pages = "402--408",

booktitle = "2007 International Conference on Field Programmable Logic and Applications",

publisher = "IEEE",

note = "2007 International Conference on Field Programmable Logic and Applications, FPL ; Conference date: 27-08-2007 Through 29-08-2007",

}

Bertels, K, Kuzmanov, G, Panainte, EM, Gaydadjiev, G, Yankova, Y, Sima, VM, Sigdel, K, Meeuws, R & Vassiliadis, S 2007, Hartes Toolchain Early Evaluation: Profiling, Compilation and HDL Generation. in 2007 International Conference on Field Programmable Logic and Applications., 4380680, IEEE, pp. 402-408, 2007 International Conference on Field Programmable Logic and Applications, FPL, Amsterdam, Netherlands, 27/08/2007. https://doi.org/10.1109/FPL.2007.4380680

TY - GEN

T1 - Hartes Toolchain Early Evaluation

T2 - 2007 International Conference on Field Programmable Logic and Applications, FPL

AU - Bertels, Koen

AU - Kuzmanov, Georgi

AU - Panainte, Elena Moscu

AU - Gaydadjiev, Georgi

AU - Yankova, Yana

AU - Sima, Vlad Mihai

AU - Sigdel, Kamana

AU - Meeuws, Roel

AU - Vassiliadis, Stamatis

PY - 2007/12/1

Y1 - 2007/12/1

N2 - The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedded processor, digital signal processing and reconfigurable hardware. In this paper, we evaluate three tools from the hArtes toolchain supporting profiling, compilation, and HDL generation. These tools facilitate the HW/SW partitioning, co-design, co-verification, and co-execution of demanding embedded applications. The described tools are provided by the DelftWorkBench framework1. Experimental results on MJPEG and G721 encoder application case studies suggest overall performance improvement of 228% and 36% respectively.

AB - The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedded processor, digital signal processing and reconfigurable hardware. In this paper, we evaluate three tools from the hArtes toolchain supporting profiling, compilation, and HDL generation. These tools facilitate the HW/SW partitioning, co-design, co-verification, and co-execution of demanding embedded applications. The described tools are provided by the DelftWorkBench framework1. Experimental results on MJPEG and G721 encoder application case studies suggest overall performance improvement of 228% and 36% respectively.

UR - http://www.scopus.com/inward/record.url?scp=48149102298&partnerID=8YFLogxK

U2 - 10.1109/FPL.2007.4380680

DO - 10.1109/FPL.2007.4380680

M3 - Conference contribution

AN - SCOPUS:48149102298

SN - 978-1-4244-1059-0

SP - 402

EP - 408

BT - 2007 International Conference on Field Programmable Logic and Applications

PB - IEEE

Y2 - 27 August 2007 through 29 August 2007

ER -

Hartes Toolchain Early Evaluation: Profiling, Compilation and HDL Generation

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