High-bandwidth Address Generation Unit

Carlo Galuzzi*, Chunyang Gou, Humberto Calderon, Georgi N. Gaydadjiev, Stamatis Vassiliadis

*Corresponding author for this work

Research output: Contribution to journalArticleAcademicpeer-review

4 Citations (Scopus)
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Abstract

In this paper we present an efficient data fetch circuitry to retrieve several operands from a n-way parallel memory system in a single machine cycle. The proposed address generation unit operates with an improved version of the low-order parallel memory access approach. Our design supports data structures of arbitrary lengths and different odd strides. The experimental results show that our address generation unit is capable of generating eight 32 -aEuro parts per thousand bit addresses every 6 ns for different strides when implemented on a VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using only trivial hardware resources.

Original languageEnglish
Pages (from-to)33-44
Number of pages12
JournalJournal of vlsi signal processing systems for signal image and video technology
Volume57
Issue number1
DOIs
Publication statusPublished - Oct-2009
Externally publishedYes
Event7th SAMOS International Workshop - Samos, Greece
Duration: 16-Jul-200719-Jul-2007

Keywords

  • Address generation unit
  • Parallel memory
  • Stride
  • MEMORY SYSTEM
  • VECTOR
  • ACCESS
  • COMPUTER

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