High-Bandwidth Address Generation Unit

Humberto Calderón*, Carlo Galuzzi, Georgi Gaydadjiev, Stamatis Vassiliadis

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

In this paper we describe an efficient data fetch circuitry for retrieving several operands from a n-bank interleaved memory system in a single machine cycle. The proposed address generation (AGEN) unit operates with a modified version of the low-order-interleaved memory access approach. Our design supports data structures with arbitrary lengths and different (odd) strides. A detailed discussion of the 32-bit AGEN design aimed at multiple-operand functional units is presented. The experimental results indicate that our AGEN is capable of producing 8 × 32-bit addresses every 6 ns for different stride cases when implemented on VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using trivial hardware resources.

Original languageEnglish
Title of host publicationEmbedded Computer Systems
Subtitle of host publicationArchitectures, Modeling, and Simulation
EditorsStamatis Vassiliadis, Mladen Bereković, Timo D. Hämäläinen
PublisherSpringer
Pages251-262
Number of pages12
ISBN (Electronic)978-3-540-73625-7
ISBN (Print)978-3-540-73622-6
DOIs
Publication statusPublished - 1-Dec-2007
Externally publishedYes
Event7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2007 - Samos, Greece
Duration: 16-Jul-200719-Jul-2007

Publication series

NameLecture Notes in Computer Science
PublisherSpringer
Volume4599
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2007
CountryGreece
CitySamos
Period16/07/200719/07/2007

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