Low-power Asynchronous Comparator with Current Feedback for Emerging-Memory-based Computing

This paper presents a low-power asynchronous comparator specifically designed for integration with emerging memory devices in analog hardware accelerators for spiking neural networks. The comparator was originally designed to address the stringent requirements of ferroelectric-based neurons, which demand asynchronous operation, ultra-low static power consumption, fast switching capabilities, and minimal input capacitance to avoid perturbation of neural dynamics. The proposed design employs current feedback techniques integrated into an operational transconductance amplifier (OTA) architecture, enabling subthreshold operation with tail currents in the order of pA while providing high current drive capability during transitions. The comparator achieves high energy efficiency with an average static power consumption of 47 pW and dynamic energy consumption of 3 fJ per operation. Statistical analysis on 360 circuits across 180 dies demonstrates robust performance characteristics. The measured performance establishes new benchmarks for asynchronous comparators in neuromorphic applications, demonstrating six orders of magnitude improvement in static power consumption compared to existing static comparator designs.