Manifestation of Precharge Faults in High Speed DRAM Devices

Zaid Al-Ars; Said Hamdioui; Georgi Gaydadjiev

doi:10.1109/DDECS.2007.4295277

Manifestation of Precharge Faults in High Speed DRAM Devices

Zaid Al-Ars^*, Said Hamdioui, Georgi Gaydadjiev

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result in their own set of faults, and increase the complexity of already known faults. This paper describes the influence of bit line coupling on precharge faults, where the memory is rendered unable to set the proper precharge voltages at the end of each operation, which causes the memory to fail in subsequent read operations. This kind of bit line coupling effect on precharge behavior has been observed in high speed DRAMs at Qimonda. This paper gives a detailed analysis of the problem, and suggests effective tests to detect it. The paper also describes the results of an industrial test evaluation on actual DRAMs chips, performed to validate the effectiveness of the proposed tests.

Original language	English
Title of host publication	2007 IEEE Design and Diagnostics of Electronic Circuits and Systems
Publisher	IEEE
Pages	179-184
Number of pages	6
ISBN (Print)	9781424411610
DOIs	https://doi.org/10.1109/DDECS.2007.4295277
Publication status	Published - 1-Dec-2007
Externally published	Yes
Event	2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS - Krakow, Poland Duration: 11-Apr-2007 → 13-Apr-2007

Conference

Conference	2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS
Country/Territory	Poland
City	Krakow
Period	11/04/2007 → 13/04/2007

Keywords

Bit line coupling
Fault modeling
High speed DRAMs
Memory testing
Precharge faults
Test evaluation

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10.1109/DDECS.2007.4295277

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Cite this

@inproceedings{caf21255297f4cc1a4c49353bf65b820,

title = "Manifestation of Precharge Faults in High Speed DRAM Devices",

abstract = "High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result in their own set of faults, and increase the complexity of already known faults. This paper describes the influence of bit line coupling on precharge faults, where the memory is rendered unable to set the proper precharge voltages at the end of each operation, which causes the memory to fail in subsequent read operations. This kind of bit line coupling effect on precharge behavior has been observed in high speed DRAMs at Qimonda. This paper gives a detailed analysis of the problem, and suggests effective tests to detect it. The paper also describes the results of an industrial test evaluation on actual DRAMs chips, performed to validate the effectiveness of the proposed tests.",

keywords = "Bit line coupling, Fault modeling, High speed DRAMs, Memory testing, Precharge faults, Test evaluation",

author = "Zaid Al-Ars and Said Hamdioui and Georgi Gaydadjiev",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/DDECS.2007.4295277",

language = "English",

isbn = "9781424411610",

pages = "179--184",

booktitle = "2007 IEEE Design and Diagnostics of Electronic Circuits and Systems",

publisher = "IEEE",

note = "2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS ; Conference date: 11-04-2007 Through 13-04-2007",

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T1 - Manifestation of Precharge Faults in High Speed DRAM Devices

AU - Al-Ars, Zaid

AU - Hamdioui, Said

AU - Gaydadjiev, Georgi

PY - 2007/12/1

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N2 - High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result in their own set of faults, and increase the complexity of already known faults. This paper describes the influence of bit line coupling on precharge faults, where the memory is rendered unable to set the proper precharge voltages at the end of each operation, which causes the memory to fail in subsequent read operations. This kind of bit line coupling effect on precharge behavior has been observed in high speed DRAMs at Qimonda. This paper gives a detailed analysis of the problem, and suggests effective tests to detect it. The paper also describes the results of an industrial test evaluation on actual DRAMs chips, performed to validate the effectiveness of the proposed tests.

AB - High speed DRAMs today suffer from an increased sensitivity to interference and noise problems. Signal integrity issues, caused by bit line and word line coupling, result in their own set of faults, and increase the complexity of already known faults. This paper describes the influence of bit line coupling on precharge faults, where the memory is rendered unable to set the proper precharge voltages at the end of each operation, which causes the memory to fail in subsequent read operations. This kind of bit line coupling effect on precharge behavior has been observed in high speed DRAMs at Qimonda. This paper gives a detailed analysis of the problem, and suggests effective tests to detect it. The paper also describes the results of an industrial test evaluation on actual DRAMs chips, performed to validate the effectiveness of the proposed tests.

KW - Bit line coupling

KW - Fault modeling

KW - High speed DRAMs

KW - Memory testing

KW - Precharge faults

KW - Test evaluation

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U2 - 10.1109/DDECS.2007.4295277

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SN - 9781424411610

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BT - 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

PB - IEEE

T2 - 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

Y2 - 11 April 2007 through 13 April 2007

ER -

Manifestation of Precharge Faults in High Speed DRAM Devices

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