Memory testing with a RISC microcontroller

Ad Van De Goor; Georgi Gaydadjiev; Said Hamdioui

doi:10.1109/DATE.2010.5457210

Memory testing with a RISC microcontroller

Ad Van De Goor^*, Georgi Gaydadjiev, Said Hamdioui

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

26 Citations (Scopus)

Abstract

Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not have memory BIST, the CPU will be the only resource to perform at least the Power-On tests. This paper shows the problems, solutions and limitations of CPU-based at-speed memory testing, illustrated with examples from the ATMEL RISC microcontroller.

Original language	English
Title of host publication	2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
Publisher	IEEE
Pages	214-219
Number of pages	6
ISBN (Electronic)	978-3-9810801-6-2
ISBN (Print)	978-1-4244-7054-9
DOIs	https://doi.org/10.1109/DATE.2010.5457210
Publication status	Published - 9-Jun-2010
Externally published	Yes
Event	Design, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany Duration: 8-Mar-2010 → 12-Mar-2010

Publication series

Name	Proceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)	1530-1591
ISSN (Electronic)	1558-1101

Conference

Conference	Design, Automation and Test in Europe Conference and Exhibition, DATE 2010
Country/Territory	Germany
City	Dresden
Period	08/03/2010 → 12/03/2010

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Cite this

@inproceedings{362ffedf0e084720938a34650d8374e4,

title = "Memory testing with a RISC microcontroller",

abstract = "Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not have memory BIST, the CPU will be the only resource to perform at least the Power-On tests. This paper shows the problems, solutions and limitations of CPU-based at-speed memory testing, illustrated with examples from the ATMEL RISC microcontroller.",

author = "{Van De Goor}, Ad and Georgi Gaydadjiev and Said Hamdioui",

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doi = "10.1109/DATE.2010.5457210",

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pages = "214--219",

booktitle = "2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)",

note = "Design, Automation and Test in Europe Conference and Exhibition, DATE 2010 ; Conference date: 08-03-2010 Through 12-03-2010",

}

Van De Goor, A, Gaydadjiev, G & Hamdioui, S 2010, Memory testing with a RISC microcontroller. in 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)., 5457210, Proceedings -Design, Automation and Test in Europe, DATE, IEEE, pp. 214-219, Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, Dresden, Germany, 08/03/2010. https://doi.org/10.1109/DATE.2010.5457210

Memory testing with a RISC microcontroller. / Van De Goor, Ad; Gaydadjiev, Georgi; Hamdioui, Said.
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 2010. p. 214-219 5457210 (Proceedings -Design, Automation and Test in Europe, DATE).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

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AU - Gaydadjiev, Georgi

AU - Hamdioui, Said

PY - 2010/6/9

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N2 - Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not have memory BIST, the CPU will be the only resource to perform at least the Power-On tests. This paper shows the problems, solutions and limitations of CPU-based at-speed memory testing, illustrated with examples from the ATMEL RISC microcontroller.

AB - Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not have memory BIST, the CPU will be the only resource to perform at least the Power-On tests. This paper shows the problems, solutions and limitations of CPU-based at-speed memory testing, illustrated with examples from the ATMEL RISC microcontroller.

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T3 - Proceedings -Design, Automation and Test in Europe, DATE

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BT - 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)

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T2 - Design, Automation and Test in Europe Conference and Exhibition, DATE 2010

Y2 - 8 March 2010 through 12 March 2010

ER -

Memory testing with a RISC microcontroller

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