Multi-Level FeFET-Based CAM Address Decoder

Address decoders are an integral part of random access memories. They are typically implemented using fast logic optimised for low latency. The latter, however, are difficult to test, while their repair is considered to be impossible. In this work we propose a highly scalable and testable address decoder solution, based on Content-Addressable Memories build with ferroelectric transistors (FeFET). Our solution has a transistor count close to the state of the art, while outperforms it in terms of latency. Due to its regular 2D structure, our proposal's testability is comparable to that of memory arrays. Moreover, adding a few spare rows will enable end-of-production repair, in the presence of manufacturing defects. By additionally increasing the number of address bits stored in a single FeFET CAM cell, potential area reductions of 30% - compared to the traditional dynamic NAND decoders - can be achieved.