Precise Identification of Memory Faults Using Electrical Simulation

Zaid Al-Ars; Said Hamdioui; Georgi Gaydadjiev

doi:10.1109/IDT.2007.4437417

Precise Identification of Memory Faults Using Electrical Simulation

Zaid Al-Ars^*, Said Hamdioui, Georgi Gaydadjiev

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Recently, a framework describing the space of all fault models has been established. Subsequently, it has been shown that many new faults of that space do exist. Gradually, The number and complexity of observed memory fault models has been gradually increasing. As a result, it has become increasingly difficult to identify the precise functional fault models that a memory suffers from. This paper shows that there are two types of possible imprecision in describing faults: underspecification, which leads to tests with insufficient fault coverage, and over specification, which leads to time-inefficient tests. A general method is presented to analyze faulty memory behavior based on electrical simulation and map it precisely onto the corresponding fault models, which makes it possible to generate time-optimal tests with optimal fault coverage.

Original language	English
Title of host publication	2007 2nd International Design and Test Workshop
Publisher	IEEE
Pages	3-8
Number of pages	6
ISBN (Electronic)	978-1-4244-1825-1
ISBN (Print)	978-1-4244-1824-4
DOIs	https://doi.org/10.1109/IDT.2007.4437417
Publication status	Published - 1-Dec-2007
Externally published	Yes
Event	2nd international Design and Test Workshop, IDT 2007 - Cairo, Egypt Duration: 16-Dec-2007 → 18-Dec-2007

Conference

Conference	2nd international Design and Test Workshop, IDT 2007
Country/Territory	Egypt
City	Cairo
Period	16/12/2007 → 18/12/2007

Keywords

Fault coverage
Fault identification
Memory fault models
Precise faults
Test time

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10.1109/IDT.2007.4437417

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Cite this

@inproceedings{c07174436294414dbb86a57aa25200f4,

title = "Precise Identification of Memory Faults Using Electrical Simulation",

abstract = "Recently, a framework describing the space of all fault models has been established. Subsequently, it has been shown that many new faults of that space do exist. Gradually, The number and complexity of observed memory fault models has been gradually increasing. As a result, it has become increasingly difficult to identify the precise functional fault models that a memory suffers from. This paper shows that there are two types of possible imprecision in describing faults: underspecification, which leads to tests with insufficient fault coverage, and over specification, which leads to time-inefficient tests. A general method is presented to analyze faulty memory behavior based on electrical simulation and map it precisely onto the corresponding fault models, which makes it possible to generate time-optimal tests with optimal fault coverage.",

keywords = "Fault coverage, Fault identification, Memory fault models, Precise faults, Test time",

author = "Zaid Al-Ars and Said Hamdioui and Georgi Gaydadjiev",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/IDT.2007.4437417",

language = "English",

isbn = "978-1-4244-1824-4",

pages = "3--8",

booktitle = "2007 2nd International Design and Test Workshop",

publisher = "IEEE",

note = "2nd international Design and Test Workshop, IDT 2007 ; Conference date: 16-12-2007 Through 18-12-2007",

}

TY - GEN

T1 - Precise Identification of Memory Faults Using Electrical Simulation

AU - Al-Ars, Zaid

AU - Hamdioui, Said

AU - Gaydadjiev, Georgi

PY - 2007/12/1

Y1 - 2007/12/1

N2 - Recently, a framework describing the space of all fault models has been established. Subsequently, it has been shown that many new faults of that space do exist. Gradually, The number and complexity of observed memory fault models has been gradually increasing. As a result, it has become increasingly difficult to identify the precise functional fault models that a memory suffers from. This paper shows that there are two types of possible imprecision in describing faults: underspecification, which leads to tests with insufficient fault coverage, and over specification, which leads to time-inefficient tests. A general method is presented to analyze faulty memory behavior based on electrical simulation and map it precisely onto the corresponding fault models, which makes it possible to generate time-optimal tests with optimal fault coverage.

AB - Recently, a framework describing the space of all fault models has been established. Subsequently, it has been shown that many new faults of that space do exist. Gradually, The number and complexity of observed memory fault models has been gradually increasing. As a result, it has become increasingly difficult to identify the precise functional fault models that a memory suffers from. This paper shows that there are two types of possible imprecision in describing faults: underspecification, which leads to tests with insufficient fault coverage, and over specification, which leads to time-inefficient tests. A general method is presented to analyze faulty memory behavior based on electrical simulation and map it precisely onto the corresponding fault models, which makes it possible to generate time-optimal tests with optimal fault coverage.

KW - Fault coverage

KW - Fault identification

KW - Memory fault models

KW - Precise faults

KW - Test time

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U2 - 10.1109/IDT.2007.4437417

DO - 10.1109/IDT.2007.4437417

M3 - Conference contribution

AN - SCOPUS:44949124503

SN - 978-1-4244-1824-4

SP - 3

EP - 8

BT - 2007 2nd International Design and Test Workshop

PB - IEEE

T2 - 2nd international Design and Test Workshop, IDT 2007

Y2 - 16 December 2007 through 18 December 2007

ER -

Precise Identification of Memory Faults Using Electrical Simulation

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