Precise Identification of Memory Faults Using Electrical Simulation

Zaid Al-Ars*, Said Hamdioui, Georgi Gaydadjiev

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review


Recently, a framework describing the space of all fault models has been established. Subsequently, it has been shown that many new faults of that space do exist. Gradually, The number and complexity of observed memory fault models has been gradually increasing. As a result, it has become increasingly difficult to identify the precise functional fault models that a memory suffers from. This paper shows that there are two types of possible imprecision in describing faults: underspecification, which leads to tests with insufficient fault coverage, and over specification, which leads to time-inefficient tests. A general method is presented to analyze faulty memory behavior based on electrical simulation and map it precisely onto the corresponding fault models, which makes it possible to generate time-optimal tests with optimal fault coverage.

Original languageEnglish
Title of host publication2007 2nd International Design and Test Workshop
Number of pages6
ISBN (Electronic)978-1-4244-1825-1
ISBN (Print)978-1-4244-1824-4
Publication statusPublished - 1-Dec-2007
Externally publishedYes
Event2nd international Design and Test Workshop, IDT 2007 - Cairo, Egypt
Duration: 16-Dec-200718-Dec-2007


Conference2nd international Design and Test Workshop, IDT 2007


  • Fault coverage
  • Fault identification
  • Memory fault models
  • Precise faults
  • Test time

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