TY - GEN
T1 - Transparent reconfigurable acceleration for heterogeneous embedded applications
AU - Beck, Antonio Carlos S.
AU - Rutzig, Mateus B.
AU - Gaydadjiev, Georgi
AU - Carro, Luigi
PY - 2008/8/25
Y1 - 2008/8/25
N2 - Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in a single device. Although reconfigurable architectures have already shown to be a potential solution for such systems, they just present significant speedups of very specific dataflow oriented kernels. Furthermore, reconfigurable fabric is still withheld by the need of special tools and compilers, clearly not sustaining backward software compatibility. In this paper, we propose a new technique to optimize both dataflow and control-flow oriented code in a totally transparent process, without the need of any modification in the source or binary codes. For that, we have developed a Binary Translation algorithm implemented in hardware, which works in parallel to a MIPS processor. The proposed mechanism is responsible for transforming sequences of instructions at runtime to be executed on a dynamic coarse-grain reconfigurable array, supporting speculative execution. Executing the MIBench suite, we show performance improvements of up to 2.5 times, while reducing 1.7 times the required energy, using trivial hardware resources.
AB - Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in a single device. Although reconfigurable architectures have already shown to be a potential solution for such systems, they just present significant speedups of very specific dataflow oriented kernels. Furthermore, reconfigurable fabric is still withheld by the need of special tools and compilers, clearly not sustaining backward software compatibility. In this paper, we propose a new technique to optimize both dataflow and control-flow oriented code in a totally transparent process, without the need of any modification in the source or binary codes. For that, we have developed a Binary Translation algorithm implemented in hardware, which works in parallel to a MIPS processor. The proposed mechanism is responsible for transforming sequences of instructions at runtime to be executed on a dynamic coarse-grain reconfigurable array, supporting speculative execution. Executing the MIBench suite, we show performance improvements of up to 2.5 times, while reducing 1.7 times the required energy, using trivial hardware resources.
UR - http://www.scopus.com/inward/record.url?scp=49749131907&partnerID=8YFLogxK
U2 - 10.1109/DATE.2008.4484843
DO - 10.1109/DATE.2008.4484843
M3 - Conference contribution
AN - SCOPUS:49749131907
SN - 9783981080
SN - 9789783981089
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 1208
EP - 1213
BT - Design, Automation and Test in Europe, DATE 2008
PB - IEEE
T2 - Design, Automation and Test in Europe, DATE 2008
Y2 - 10 March 2008 through 14 March 2008
ER -