A novel productivity-driven logic element for field-programmable devices

Thomas Marconi*, Koen Bertels, Georgi Gaydadjiev

*Bijbehorende auteur voor dit werk

Onderzoeksoutput: ArticleAcademicpeer review


Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements(LEs). In the conventional LE, the output of the combinational logic (e.g. the look-uptable (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal-Oxide-Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.

Originele taal-2English
Pagina's (van-tot)731-762
Aantal pagina's32
TijdschriftInternational journal of electronics
Nummer van het tijdschrift6
StatusPublished - 3-jun.-2014
Extern gepubliceerdJa

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