High-bandwidth Address Generation Unit

Carlo Galuzzi*, Chunyang Gou, Humberto Calderon, Georgi N. Gaydadjiev, Stamatis Vassiliadis

*Bijbehorende auteur voor dit werk

Onderzoeksoutput: ArticleAcademicpeer review

4 Citaten (Scopus)
19 Downloads (Pure)


In this paper we present an efficient data fetch circuitry to retrieve several operands from a n-way parallel memory system in a single machine cycle. The proposed address generation unit operates with an improved version of the low-order parallel memory access approach. Our design supports data structures of arbitrary lengths and different odd strides. The experimental results show that our address generation unit is capable of generating eight 32 -aEuro parts per thousand bit addresses every 6 ns for different strides when implemented on a VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using only trivial hardware resources.

Originele taal-2English
Pagina's (van-tot)33-44
Aantal pagina's12
TijdschriftJournal of vlsi signal processing systems for signal image and video technology
Nummer van het tijdschrift1
StatusPublished - okt.-2009
Extern gepubliceerdJa
Evenement7th SAMOS International Workshop - Samos, Greece
Duur: 16-jul.-200719-jul.-2007

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