@inproceedings{54ca13fbff3d4449b1db0fe31e0a886b,
title = "High-Bandwidth Address Generation Unit",
abstract = "In this paper we describe an efficient data fetch circuitry for retrieving several operands from a n-bank interleaved memory system in a single machine cycle. The proposed address generation (AGEN) unit operates with a modified version of the low-order-interleaved memory access approach. Our design supports data structures with arbitrary lengths and different (odd) strides. A detailed discussion of the 32-bit AGEN design aimed at multiple-operand functional units is presented. The experimental results indicate that our AGEN is capable of producing 8 × 32-bit addresses every 6 ns for different stride cases when implemented on VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using trivial hardware resources.",
author = "Humberto Calder{\'o}n and Carlo Galuzzi and Georgi Gaydadjiev and Stamatis Vassiliadis",
year = "2007",
month = dec,
day = "1",
doi = "10.1007/978-3-540-73625-7_27",
language = "English",
isbn = "978-3-540-73622-6",
series = "Lecture Notes in Computer Science",
publisher = "Springer",
pages = "251--262",
editor = "Vassiliadis, {Stamatis } and Berekovi{\'c}, {Mladen } and H{\"a}m{\"a}l{\"a}inen, {Timo D. }",
booktitle = "Embedded Computer Systems",
note = "7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2007 ; Conference date: 16-07-2007 Through 19-07-2007",
}