Memory mapping for multi-die FPGAS

Nils Voss, Pablo Quintana, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev

OnderzoeksoutputAcademicpeer review

9 Citaten (Scopus)

Samenvatting

This paper proposes an algorithm for mapping logical to physical memory resources on FPGAs. Our greedy strategy based algorithm is specifically designed to facilitate timing closure on modern multi-die FPGAs for static-dataflow accelerators utilising most of the on-chip resources. The main objective of the proposed algorithm is to ensure that specific sub-parts of the design under consideration can fully reside within a single die to limit inter-die communication. The above is achieved by performing the memory mapping for each sub-part of the design separately while keeping allocation of the available physical resources balanced. As a result the number of inter-die connections is reduced on average by 50% compared to an algorithm targeting minimal area usage for real, complex applications using most of the on-chip's resources. Additionally, our algorithm is the only one out of the four evaluated approaches which successfully produces place and route results for all 33 applications and benchmarks.

Originele taal-2English
Titel2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
UitgeverijIEEE
Pagina's78-86
Aantal pagina's9
ISBN van elektronische versie978-1-7281-1131-5
ISBN van geprinte versie978-1-7281-1132-2
DOI's
StatusPublished - 1-apr.-2019
Extern gepubliceerdJa
Evenement27th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019 - San Diego, United States
Duur: 28-apr.-20191-mei-2019

Conference

Conference27th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2019
Land/RegioUnited States
StadSan Diego
Periode28/04/201901/05/2019

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