The SARC Architecture

Alex Ramirez; Felipe Cabarcas; Ben Juurlink; Mauricio Alvarez Mesa; Friman Sanchez; Arnaldo Azevedo; Cor Meenderinck; Catalin Ciobanu; Sebastian Isaza; Georgi Gaydadjiev

doi:10.1109/MM.2010.79

The SARC Architecture

Alex Ramirez^*, Felipe Cabarcas, Ben Juurlink, Mauricio Alvarez Mesa, Friman Sanchez, Arnaldo Azevedo, Cor Meenderinck, Catalin Ciobanu, Sebastian Isaza, Georgi Gaydadjiev

^*Bijbehorende auteur voor dit werk

Onderzoeksoutput: Article › Academic › peer review

37 Citaten (Scopus)

Samenvatting

The sarc architecture is composed of multiple processor types and a set of user-managed Direct Memory Access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.

Originele taal-2	English
Pagina's (van-tot)	16-29
Aantal pagina's	14
Tijdschrift	Ieee micro
Volume	30
Nummer van het tijdschrift	5
DOI's	https://doi.org/10.1109/MM.2010.79
Status	Published - 2010
Extern gepubliceerd	Ja

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